The present invention relates, in general, to a nonvolatile semiconductor memory employing a ferroelectric material and more particularly to a ferroelectric memory which is capable of holding the newest information as the nonvolatile information and of realizing high integration, high reliability and high speed operation.
A ferroelectric random access memory (herein-after, referred to as "an FERAM" for short, when applicable) employing a ferroelectric material is a nonvolatile memory which operates to store the information therein on the basis of the polarization state of ferroelectric materials. However, in the prior art ferroelectric memory, the polarization is switched in the operation of reading out the information as well as in the operation of writing the information, causing fatigue in a film made of a ferroelectric material. As a result, there arises a problem that the permitted number of accesses with respect to the rewrite and read of the information is remarkably limited as compared with the dynamic random access memories (the DRAMs) for example. In addition, there arises another problem that since a fixed period of time is required for the switch of the polarization, the operation time is necessarily delayed.
As for the method of solving the problems of the fatigue of the ferroelectric film and the reduction of the read speed which occur along with the switch of the polarization, the following method is proposed in JP-A-3-283176. That is, as shown in an array configuration of FIG. 2, in the normal operation, the electric potential on a plate line is made Vcc for example so that the FERAM is used as the DRAM, and before the power supply has been turned off, on the basis of the write operation by the FERAM, the information of interest is stored in the form of nonvolatile information. If the electric potential on the plate line is made Vcc, in the case where the electric potential at the storage node is either 0 V or Vcc, the polarization is not inverted at all. Therefore, the problem of the fatigue of the ferroelectric capacitor can be effectively prevented and also the reduction of the read speed does not occur. Next, when turning the power supply on, if the non-volatile information is read out on the basis of the read operation by the FERAM, the FERAM can be substantially operated as the nonvolatile memory.
However, in the above-mentioned memory with both DRAM and FERAM modes, there arises still another problem that the operation of converting the volatile information into the nonvolatile information is complicated. That is, it is necessary that with respect to all the memory cells, after the information is first read out on the basis of the operation by DRAMs, in correspondence to that information thus read out, that information is stored in the form of nonvolatile information on the basis of the FERAM operation. In particular, in the case where the power source assumes the off state due to unexpected trouble, it is very difficult to speedily complete the above-mentioned conversion operation. For the period of time when in the above-mentioned system, the ferroelectric memory is used as the DRAM, all the polarization of the ferroelectric material is arranged in one direction. Therefore, all the stored information is erased along with the unexpected off state of the power supply.
The present invention was made in order to overcome the above-mentioned problems associated with the prior art ferroelectric memory and it is therefore an object of the present invention to provide a highly reliable and high speed nonvolatile memory (a ferroelectric memory) having high degree of integration which, while constituted by one transistor and one capacitor in the same way as that in the DRAM, is capable of mitigating the fatigue of a ferroelectric capacitor due to the polarization switch and of holding the newest information in the form of nonvolatile information even in the case where the power supply is forced to be turned off due to the unexpected trouble.
It is another object of the present invention to provide a highly reliable and high speed nonvolatile memory (a ferroelectric memory) with high degree of integration which has the same memory cell configuration as that of the static random access memories (the SRAMs).
In order to attain the above-mentioned objects, in a semiconductor memory having a plurality of memory cells each constituted by at least one transistor and one ferroelectric capacitor, the ferroelectric memory according to the present invention has means (constituted by a precharge circuit, a circuit for detecting a power supply voltage, a circuit for supplying a plate electric potential, and the like) for performing, as a nonvolatile memory, e.g., a DRAM, the read and write operations in a normal state and for making speedily a plate electric potential the ground electric potential (0 V) in an off state of a power supply. The plate electric potential is set to Vcc/2 and a data line precharge electric potential in the read operation is also set to Vcc/2. In addition, a configuration is possibly designed in such a way that the plate is common to only the memory cells connected to the common word line (the configuration having a plurality of plate lines) in order to further improve the reliability of the ferroelectric memory, or alternatively the above-mentioned means is included in SRAMs.
Incidentally, the present ferroelectric memory is suitable for a system in which the number of read operations is larger than the number of rewrite operations, e.g., a system which is applied to the storage of the data and the program itself in the case where the calculation is carried out forward on the basis of the program.
In the present invention, the read operation is performed by detecting the voltage of the storage node in the same way as that in volatile memories, e.g., DRAMs. As a result of the effect in which both the plate electric potential and the data line precharge electric potential are set to Vcc/2, both the voltage detection and the subsequent amplification are performed without being accompanied by the polarization switch. Therefore, the fatigue of the ferroelectric film and the reduction of the read speed can be effectively prevented. In addition, in the polarization state of the ferroelectric materials, the newest information which has been obtained by the most recent rewrite is held. In other words, the volatile information as the storage node electric potential and the nonvolatile information as the polarization state of the ferroelectric film always coincide with each other. Although the rewrite operation is accompanied by the polarization switch, the limit of the number of rewrite operation is estimated to be equal to or larger than 10.sup.11 times which is larger by far than 10.sup.6 times, i.e., the limit which is considered in the electrically erasable and programmable read only memory (the EEPROM) for example. Therefore, the ferroelectric memory according to the present invention can be applied to many systems without any problem. For example, the ferroelectric memory according to the present invention can be applied to the operation of storing the data and the program itself, and the like, in the case where the calculation, in which in general, the number of read operation is larger than the number of rewrite operations, is carried out forward on the basis of the program. Means is provided which operates to, in the off state of the power supply, before the electric potential at the storage node is dropped from Vcc down to 0 V, drop speedily the plate electric potential from Vcc/2 down to 0 V, whereby the polarization state is surely held, and it is possible to leave the newest nonvolatile information which has been obtained by the most recent rewrite operation. Next, when turning the power supply on, if in accordance with the read operation by the FERAM, the nonvolatile information which was stored in the form of the polarization state of the ferroelectric film is amplified through the associated data line, the nonvolatile information of interest can be converted into the volatile information as the electric potential at the storage node. That is, it is possible to realize the high reliable and high speed nonvolatile memory having the high degree of integration.